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Use of Reconfigurable Elements in the Design and Validation of Multiprocessors

Nemzetközi (egyéb) project
1997 - 1999

Local supervisor: Pataricza András
Official project supervisor: BME MIT FTSRG

Different abstract mathematical models, like dataflow networks, Petri-nets, process algebra are used in the functional and dependability validation of digital systems. These modeling paradigms share the very same key problem of state reachability analysis for instance to decide, whether a system will enter into an unsafe state.
Potential performance bottlenecks in the handling of large scale systems during the verification can be identified. Monoprocessor algorithms require either radical model (over) simplifications or long run times in the case of complex target systems.
Although the computational power of modern computing equipment increases rapidly even accompanied by a radical drop in the price/performance ratio, the huge processing capacity is insufficient for many practical applications.
The traditional solutions to overcome this performance bottleneck can be grouped into the following typical categories:

  • Multiprocessor systems
  • Co-processors (application dependent dedicated hardware subunits)
  • Accelerators (complete parts of the problem are realized on the FPGA)
All of the above mentioned solution alternatives are favorite candidates for the use in modeling and validation of digital systems, as the underlying mathematical models are hierarchically composed of very simple components like transition and places in Petri-nets.
These technologies are examined in the framework of the projects. The results are compared against those with the realization by mono- and multiprocessor systems.

Partners:

  • Department of Computer Structures, University of Erlangen, Germany

Further information about the project:
Official homepage: http://www.inf.mit.bme.hu/FTSRG/Projects/accuse99.html
Department homepage: http://www.mit.bme.hu/projects/accuse/
Official email address: pataric@mit.bme.hu